1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and, in particular, to trim bit circuits utilizable for trimming a band-gap reference circuit to ideal voltage.
2. Discussion of the Related Art
The band-gap reference circuit has been a popular analog integrated circuit for many years. It is used in conventional junction-isolated bipolar integrated circuit technology to provide a stable low-voltage reference. Band-gap circuits are also used in digital integrated circuits to provide a local bias that is not adversely affected by ambient noise or transients.
Operationally, band-gap reference circuits rely on the summation of a first voltage term that decreases at the rate of about xe2x88x922 millivolts/xc2x0 C. and a second voltage that increases at about +2 millivolts/xc2x0 C., thereby resulting in an overall temperature coefficient (tempco) for the circuit that is substantially zero.
All band-gap circuits utilize this summation of a growing voltage and a shrinking voltage to generate a stable, low-tempco reference voltage. It has also been shown that, when a band-gap circuit has been trimmed to the correct voltage, the correct tempco will follow, despite process variations in parameters such as Vbe, beta, sheet resistivity, etc. consequently, band-gap circuits are often trimmed to their ideal voltage to provide a low tempco.
The present invention provides a trim bit circuit that uses a cascoded differential PMOS EPROM with a fixed offset cross-coupled latch. The output sense signal is transferred by transmission gates to NMOS latched inverters. The output is buffered by a third inverter. Programming is performed by an NMOS current sink that pulls the drain of the programmed (trimmed) PMOS EPROM device to ground. This places the full positive supply across the short channel trimmed device, the punchthrough inducing a trapped charge on the device. The reference (untrimmed) PMOS EPROM device is uncharged. Thus, the two PMOS EPROM transistors have unequal current. During the read mode, a replication bias voltage is induced by an external xe2x80x9creadxe2x80x9d power-on-reset circuit, thereby placing a few volts below positive supply on the gates of the cascode devices. This allows the Vds of the PMOS EPROM devices to increase to a little less than a volt. Since the trimmed transistor has more current than the untrimmed transistor by a few decades of current, the drain of the load latch transistor rises to a voltage limited by the saturation voltage of the EPROM devices, causing the output of the load latch device to be high.
Further features and advantages of the present invention will become apparent from the following detailed description and accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.